1. Field of the Invention
The present disclosure generally relates to semiconductor device structures formed in and above SOI (semiconductor-on-insulator) substrates having a buried insulating multilayer structure and to the fabrication of a wafer with an SOI structure having a buried insulating multilayer structure, and, particularly, to flash non-volatile floating back bias in such SOI semiconductor devices.
2. Description of the Related Art
In the technology of computer data storage, storage or memory devices are generally distinguished by non-volatile memory and volatile memory devices. Volatile memory devices, as opposed to non-volatile memory devices, require constant power to maintain the stored information and are often implemented in the form of dynamic random access memory (DRAM) or static random access memory (SRAM) devices. In contrast, non-volatile memory devices retain the stored information even when not constantly supplied with electric power. Accordingly, non-volatile memory devices are suitable for long-term storage of information. An example of an electronic non-volatile computer storage medium is given by flash memory, which was originally developed from electrically erasable programmable read only memory (EEPROM). In a more recent application, flash memories are used as a replacement for hard discs. Since flash memory does not have the mechanical limitations and latencies of hard drives, so-called “solid state drives (SSDs)” are attractive when considering speed, noise, power consumption and reliability relative to traditional hard drives. Accordingly, flash drives are gaining in popularity as mobile device secondary storage devices and as substitutes for hard drives in high performance desktop computers.
Recent approaches to non-volatile computer memory are closely related to flash RAM, i.e., in the form of silicon-oxide-nitride-oxide-silicon (SONOS) structures, representing one of a charge trap flash variant. SONOS structures promise lower programming voltages and higher program/erase cycle endurance when compared to polysilicon-based flash devices. Currently, SONOS is an area of active research and development effort.
A SONOS memory device generally uses a silicon nitride layer with traps as a charge storage layer. The traps in the charge storage layer (silicon nitride) capture charge carriers injected from a channel of a MOS transistor and retain the charge. Therefore, this type of memory is also known as a so-called “charge trap memory.” Since the charge storage layer (silicon nitride) is an insulator, this storage mechanism is inherently less sensitive to pinhole defects and is more robust in terms of yield and data retention. Since a SONOS transistor shares many of the key process steps implemented in current CMOS transistors, many regions of a SONOS transistor, i.e., source, drain and gate, are identical to those of a common CMOS transistor. Consequently, the process architecture of embedded SONOS technologies is given by the known process architecture of CMOS technology.
Currently, non-volatile and reconfigurable field programmable gate arrays (FPGAs) are considered as representing an attractive solution for high level system integration in various applications, such as aerospace and military applications. Unlike SRAM-based FPGAs, the configuration memories are not volatile and, hence, do not require additional non-volatile memory to reload the device configuration data at system power-up or due to radiation effects in addition to triple module redundancy (TMR) of its entire set of configuration bits.
With the continuous scaling down of device dimensions to increasingly small technology nodes at 28 nm and beyond, various issues and challenges arise. For example, precise control of the electrical conductivity of the channel of a MOS transistor is difficult to maintain at very small process geometries. Since the switching behavior of a MOSFET is characterized by the threshold voltage (Vt) of a MOSFET, the precise setting of a definition and control of the threshold voltage (Vt) throughout the fabrication process of semiconductor devices is essential for achieving optimal power consumption and performance of semiconductor device structures. In general, there are several factors which control the threshold voltage (Vt), such as the gate oxide thickness, the work function of the gate, and the channel doping, mainly representing independent factors. The scaling of a semiconductor device to more advanced technology nodes led to faster switching and higher current drive behaviors or advanced semiconductor devices, at the expense, however, of a decreased noise margin, increased leakage current and increased power.
It is, therefore, desirable to control the threshold voltage (Vt) of advanced semiconductor devices at advanced technology nodes, and to provide semiconductor device structures that allow for adjustment and tuning of the threshold voltage (Vt), particularly in flash memory technologies.